[VIP第3年] 指数:1
8.14 SPI0/1
All SPI functions are movable functions and are assigned to pins through the switch
matrix.
8.14.1 Features
• Maximum data rates of up to 30 Mbit/s in master mode and up to 18 Mbit/s in slave
mode for SPI functions connected to all digital pins except the open-drain pins.
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data, which can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data, which allows very
versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
8.15 I2C-bus interface (I2C0/1/2/3)
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
– Pin interrupts can wake up the LPC82x from sleep mode, deep-sleep mode, and
power-down mode.
• Pin interrupt pattern match engine
– Up to eight pins can be selected from all digital pins to contribute to a boolean
expression. The boolean expression consists of specified levels and/or transitions
on various combinations of these pins.
– Each minterm (product term) comprising the specified boolean expression can
generate its own, dedicated interrupt request.
– Any occurrence of a pattern match can be also programmed to generate an RXEV
notification to the ARM CPU. The RXEV signal can be connected to a pin.
– The pattern match engine does not facilitate wake-up.
8.12 DMA controller
The DMA controller can access all memories and the USART, SPI, I2C, and ADC
peripherals using DMA requests or triggers. DMA transfers can also be triggered by
internal events like the ADC interrupts, the pin interrupts (PININT0 and PININT1), the
SCTimer DMA requests, and the DMA trigger outputs.
8.12.1 Features
• 18 channels with each channel connected to peripheral request inputs.
• DMA operations can be triggered by on-chip events or by two pin interrupts. Each
DMA channel can select one trigger input from 9 sources.
• Priority is user selectable for each channel.
• Continuous priority arbitration.
• Address cache with two entries.
• Efficient use of data bus.
• Supports single transfers up to 1,024 words.
• Address increment options allow packing and/or unpacking data
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